HAL2 Migrator
LL SPI APIs listing for migration ¶
There are a few API changes in the LL layer. This page lists only the modified LL APIs. Others not listed here are unchanged between HAL1 and HAL2.
LL SPI constants ¶
|
HAL1 |
series |
HAL2 |
|---|---|---|
|
LL_SPI_GRP1_GPDMA_CH1_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP1_GPDMA1_CH1_TC |
|
LL_SPI_GRP1_GPDMA_CH2_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP1_GPDMA1_CH2_TC |
|
LL_SPI_GRP1_GPDMA_CH3_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP1_GPDMA1_CH3_TC |
|
LL_SPI_GRP1_EXTI4_TRG |
u5 |
LL_SPI_TRIG_GRP1_EXTI4 |
|
LL_SPI_GRP1_EXTI9_TRG |
u5 |
LL_SPI_TRIG_GRP1_EXTI9 |
|
LL_SPI_GRP1_LPTIM1_CH1_TRG |
u5 |
LL_SPI_TRIG_GRP1_LPTIM1_CH1 |
|
LL_SPI_GRP1_LPTIM2_CH1_TRG |
u5 |
LL_SPI_TRIG_GRP1_LPTIM2_CH1 |
|
LL_SPI_GRP1_COMP1_TRG |
u5 |
LL_SPI_TRIG_GRP1_COMP1_OUT |
|
LL_SPI_GRP1_COMP2_TRG |
u5 |
LL_SPI_TRIG_GRP1_COMP2_OUT |
|
LL_SPI_GRP1_RTC_ALRA_TRG |
u5 |
LL_SPI_TRIG_GRP1_RTC_ALRA_TRG |
|
LL_SPI_GRP1_RTC_WUT_TRG |
u5 |
LL_SPI_TRIG_GRP1_RTC_WUT_TRG |
|
LL_SPI_GRP2_LPDMA_CH0_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP2_LPDMA1_CH0_TC |
|
LL_SPI_GRP2_LPDMA_CH1_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP2_LPDMA1_CH1_TC |
|
LL_SPI_GRP2_LPDMA_CH2_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP2_LPDMA1_CH2_TC |
|
LL_SPI_GRP2_LPDMA_CH3_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP2_LPDMA1_CH3_TC |
|
LL_SPI_GRP2_EXTI4_TRG |
u5 |
LL_SPI_TRIG_GRP2_EXTI4 |
|
LL_SPI_GRP2_EXTI8_TRG |
u5 |
LL_SPI_TRIG_GRP2_EXTI8 |
|
LL_SPI_GRP1_GPDMA_CH0_TCF_TRG |
u5 |
LL_SPI_TRIG_GRP1_GPDMA1_CH0_TC |
|
LL_SPI_TRIG_POLARITY_FALLING |
u5 |
LL_SPI_AM_TRIG_FALLING |
|
LL_SPI_GRP2_RTC_WUT_TRG |
u5 |
LL_SPI_TRIG_GRP2_RTC_WUT_TRG |
|
LL_SPI_GRP2_COMP2_TRG |
u5 |
LL_SPI_TRIG_GRP2_COMP2_OUT |
|
LL_SPI_GRP2_COMP1_TRG |
u5 |
LL_SPI_TRIG_GRP2_COMP1_OUT |
|
LL_SPI_GRP2_LPTIM3_CH1_TRG |
u5 |
LL_SPI_TRIG_GRP2_LPTIM3_CH1 |
|
LL_SPI_GRP2_LPTIM1_CH1_TRG |
u5 |
LL_SPI_TRIG_GRP2_LPTIM1_CH1 |
|
LL_SPI_TRIG_POLARITY_RISING |
u5 |
LL_SPI_AM_TRIG_RISING |
|
LL_SPI_DMA_PARITY_ODD |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_DMA_PARITY_EVEN |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_TX_FIFO_FULL |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_TX_FIFO_HALF_FULL |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_TX_FIFO_QUARTER_FULL |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_TX_FIFO_EMPTY |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_RX_FIFO_FULL |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_RX_FIFO_HALF_FULL |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_RX_FIFO_QUARTER_FULL |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_RX_FIFO_EMPTY |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_RX_FIFO_TH_QUARTER |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_RX_FIFO_TH_HALF |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
LL_SPI_CR2_ERRIE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_CR2_TXEIE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_CR2_RXNEIE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_SR_FRE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_SR_RXNE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_SR_TXE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_SR_BSY |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_SR_CRCERR |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
LL_SPI_SR_RXWNE |
u5, h5, h7 |
LL_SPI_FLAG_RXWNE |
|
LL_SPI_SR_TXC |
u5, h5, h7 |
LL_SPI_FLAG_TXC |
|
LL_SPI_SR_SUSP |
u5, h5, h7 |
LL_SPI_FLAG_SUSP |
|
LL_SPI_SR_TIFRE |
u5, h5, h7 |
LL_SPI_FLAG_TIFRE |
|
LL_SPI_SR_OVR |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_FLAG_OVR |
|
LL_SPI_SR_MODF |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_FLAG_MODF |
|
LL_SPI_SR_CRCE |
u5, h5, h7 |
LL_SPI_FLAG_CRCE |
|
LL_SPI_SR_UDR |
u5, h5, h7 |
LL_SPI_FLAG_UDR |
|
LL_SPI_SR_TXTF |
u5, h5, h7 |
LL_SPI_FLAG_TXTF |
|
LL_SPI_SR_EOT |
u5, h5, h7 |
LL_SPI_FLAG_EOT |
|
LL_SPI_SR_DXP |
u5, h5, h7 |
LL_SPI_FLAG_DXP |
|
LL_SPI_SR_TXP |
u5, h5, h7 |
LL_SPI_FLAG_TXP |
|
LL_SPI_SR_RXP |
u5, h5, h7 |
LL_SPI_FLAG_RXP |
|
LL_SPI_SR_TSERF |
h7 |
Not implemented yet in HAL2. |
|
LL_SPI_IER_TSERFIE |
h7 |
Not implemented yet in HAL2. |
|
LL_SPI_GRP2_RTC_ALRA_TRG |
u5 |
LL_SPI_TRIG_GRP2_RTC_ALRA_TRG |
|
LL_SPI_CRC_4BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_4_BIT |
|
LL_SPI_CRC_5BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_5_BIT |
|
LL_SPI_CRC_6BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_6_BIT |
|
LL_SPI_CRC_7BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_7_BIT |
|
LL_SPI_CRC_8BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_CRC_LENGTH_8_BIT |
|
LL_SPI_CRC_9BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_9_BIT |
|
LL_SPI_CRC_10BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_10_BIT |
|
LL_SPI_CRC_11BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_11_BIT |
|
LL_SPI_CRC_12BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_12_BIT |
|
LL_SPI_CRC_13BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_13_BIT |
|
LL_SPI_CRC_14BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_14_BIT |
|
LL_SPI_CRC_15BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_15_BIT |
|
LL_SPI_CRC_16BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_CRC_LENGTH_16_BIT |
|
LL_SPI_CRC_17BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_17_BIT |
|
LL_SPI_CRC_18BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_18_BIT |
|
LL_SPI_CRC_19BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_19_BIT |
|
LL_SPI_CRC_20BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_20_BIT |
|
LL_SPI_CRC_21BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_21_BIT |
|
LL_SPI_CRC_22BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_22_BIT |
|
LL_SPI_CRC_23BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_23_BIT |
|
LL_SPI_CRC_24BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_24_BIT |
|
LL_SPI_CRC_25BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_25_BIT |
|
LL_SPI_CRC_26BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_26_BIT |
|
LL_SPI_CRC_27BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_27_BIT |
|
LL_SPI_CRC_28BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_28_BIT |
|
LL_SPI_CRC_29BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_29_BIT |
|
LL_SPI_CRC_30BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_30_BIT |
|
LL_SPI_CRC_31BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_31_BIT |
|
LL_SPI_CRC_32BIT |
u5, h5, h7 |
LL_SPI_CRC_LENGTH_32_BIT |
|
LL_SPI_ID_IDLENESS_00CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_00CYCLE |
|
LL_SPI_ID_IDLENESS_01CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_01CYCLE |
|
LL_SPI_ID_IDLENESS_02CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_02CYCLE |
|
LL_SPI_ID_IDLENESS_03CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_03CYCLE |
|
LL_SPI_ID_IDLENESS_04CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_04CYCLE |
|
LL_SPI_ID_IDLENESS_05CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_05CYCLE |
|
LL_SPI_ID_IDLENESS_06CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_06CYCLE |
|
LL_SPI_ID_IDLENESS_07CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_07CYCLE |
|
LL_SPI_ID_IDLENESS_08CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_08CYCLE |
|
LL_SPI_ID_IDLENESS_09CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_09CYCLE |
|
LL_SPI_ID_IDLENESS_10CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_10CYCLE |
|
LL_SPI_ID_IDLENESS_11CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_11CYCLE |
|
LL_SPI_ID_IDLENESS_12CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_12CYCLE |
|
LL_SPI_ID_IDLENESS_13CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_13CYCLE |
|
LL_SPI_ID_IDLENESS_14CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_14CYCLE |
|
LL_SPI_ID_IDLENESS_15CYCLE |
u5, h5, h7 |
LL_SPI_MIDI_DELAY_15CYCLE |
|
LL_SPI_POLARITY_HIGH |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_CLOCK_POLARITY_HIGH |
|
LL_SPI_POLARITY_LOW |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_CLOCK_POLARITY_LOW |
|
LL_SPI_PHASE_2EDGE |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_CLOCK_PHASE_2EDGE |
|
LL_SPI_PHASE_1EDGE |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_CLOCK_PHASE_1EDGE |
|
LL_SPI_UDR_CONFIG_LAST_RECEIVED |
u5, h5 |
LL_SPI_UNDERRUN_CONFIG_LAST_RECEIVED |
|
LL_SPI_UDR_CONFIG_REGISTER_PATTERN |
u5, h5 |
LL_SPI_UNDERRUN_CONFIG_REGISTER_PATTERN |
|
LL_SPI_RXCRCINIT_ALL_ONES_PATTERN |
u5, h5, h7 |
LL_SPI_CRC_RX_INIT_PATTERN_ALL_ONE |
|
LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN |
u5, h5, h7 |
LL_SPI_CRC_RX_INIT_PATTERN_ALL_ZERO |
|
LL_SPI_TXCRCINIT_ALL_ONES_PATTERN |
u5, h5, h7 |
LL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE |
|
LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN |
u5, h5, h7 |
LL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO |
|
LL_SPI_UDR_CONFIG_LAST_TRANSMITTED |
h7 |
Not implemented yet in HAL2. |
|
LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME |
h7 |
Not implemented yet in HAL2. |
|
LL_SPI_UDR_DETECT_END_DATA_FRAME |
h7 |
Not implemented yet in HAL2. |
|
LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS |
h7 |
Not implemented yet in HAL2. |
|
LL_SPI_SS_IDLENESS_00CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_00CYCLE |
|
LL_SPI_SS_IDLENESS_01CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_01CYCLE |
|
LL_SPI_SS_IDLENESS_02CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_02CYCLE |
|
LL_SPI_SS_IDLENESS_03CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_03CYCLE |
|
LL_SPI_SS_IDLENESS_04CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_03CYCLE |
|
LL_SPI_SS_IDLENESS_05CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_05CYCLE |
|
LL_SPI_SS_IDLENESS_06CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_06CYCLE |
|
LL_SPI_SS_IDLENESS_07CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_07CYCLE |
|
LL_SPI_SS_IDLENESS_08CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_08CYCLE |
|
LL_SPI_SS_IDLENESS_09CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_09CYCLE |
|
LL_SPI_SS_IDLENESS_10CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_10CYCLE |
|
LL_SPI_SS_IDLENESS_11CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_11CYCLE |
|
LL_SPI_SS_IDLENESS_12CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_12CYCLE |
|
LL_SPI_SS_IDLENESS_13CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_13CYCLE |
|
LL_SPI_SS_IDLENESS_14CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_14CYCLE |
|
LL_SPI_SS_IDLENESS_15CYCLE |
u5, h5, h7 |
LL_SPI_MSSI_DELAY_15CYCLE |
|
LL_SPI_IER_TXPIE |
u5, h5, h7 |
LL_SPI_IT_TXP |
|
LL_SPI_IER_RXPIE |
u5, h5, h7 |
LL_SPI_IT_RXP |
|
LL_SPI_IER_EOTIE |
u5, h5, h7 |
LL_SPI_IT_EOT |
|
LL_SPI_IER_UDRIE |
u5, h5, h7 |
LL_SPI_IT_UDR |
|
LL_SPI_IER_DXPIE |
u5, h5, h7 |
LL_SPI_IT_DXP |
|
LL_SPI_IER_MODFIE |
u5, h5, h7 |
LL_SPI_IT_MODF |
|
LL_SPI_IER_TIFREIE |
u5, h5, h7 |
LL_SPI_IT_TIFRE |
|
LL_SPI_IER_CRCEIE |
u5, h5, h7 |
LL_SPI_IT_CRCE |
|
LL_SPI_IER_OVRIE |
u5, h5, h7 |
LL_SPI_IT_OVR |
|
LL_SPI_IER_TXTFIE |
u5, h5, h7 |
LL_SPI_IT_TXTF |
|
LL_SPI_BAUDRATEPRESCALER_BYPASS |
u5, h5, h7 |
LL_SPI_BAUD_RATE_PRESCALER_BYPASS |
|
LL_SPI_BAUDRATEPRESCALER_DIV2 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_2 |
|
LL_SPI_BAUDRATEPRESCALER_DIV4 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_4 |
|
LL_SPI_BAUDRATEPRESCALER_DIV8 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_8 |
|
LL_SPI_BAUDRATEPRESCALER_DIV16 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_16 |
|
LL_SPI_BAUDRATEPRESCALER_DIV32 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_32 |
|
LL_SPI_BAUDRATEPRESCALER_DIV64 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_64 |
|
LL_SPI_BAUDRATEPRESCALER_DIV128 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_128 |
|
LL_SPI_BAUDRATEPRESCALER_DIV256 |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_BAUD_RATE_PRESCALER_256 |
|
LL_SPI_DATAWIDTH_4BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_4BIT |
|
LL_SPI_DATAWIDTH_5BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_5BIT |
|
LL_SPI_DATAWIDTH_6BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_6BIT |
|
LL_SPI_DATAWIDTH_7BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_7BIT |
|
LL_SPI_DATAWIDTH_8BIT |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_DATA_WIDTH_8BIT |
|
LL_SPI_DATAWIDTH_9BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_9BIT |
|
LL_SPI_DATAWIDTH_10BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_10BIT |
|
LL_SPI_DATAWIDTH_11BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_11BIT |
|
LL_SPI_DATAWIDTH_12BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_12BIT |
|
LL_SPI_DATAWIDTH_13BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_13BIT |
|
LL_SPI_DATAWIDTH_14BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_14BIT |
|
LL_SPI_DATAWIDTH_15BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_15BIT |
|
LL_SPI_DATAWIDTH_16BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_16BIT |
|
LL_SPI_DATAWIDTH_17BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_17BIT |
|
LL_SPI_DATAWIDTH_18BIT |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_DATA_WIDTH_18BIT |
|
LL_SPI_DATAWIDTH_19BIT |
u5, h5, c0, l4, g4, g0, h7 |
LL_SPI_DATA_WIDTH_19BIT |
|
LL_SPI_DATAWIDTH_20BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_20BIT |
|
LL_SPI_DATAWIDTH_21BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_21BIT |
|
LL_SPI_DATAWIDTH_22BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_22BIT |
|
LL_SPI_DATAWIDTH_23BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_23BIT |
|
LL_SPI_DATAWIDTH_24BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_24BIT |
|
LL_SPI_DATAWIDTH_25BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_25BIT |
|
LL_SPI_DATAWIDTH_26BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_26BIT |
|
LL_SPI_DATAWIDTH_27BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_27BIT |
|
LL_SPI_DATAWIDTH_28BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_28BIT |
|
LL_SPI_DATAWIDTH_29BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_29BIT |
|
LL_SPI_DATAWIDTH_30BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_30BIT |
|
LL_SPI_DATAWIDTH_31BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_31BIT |
|
LL_SPI_DATAWIDTH_32BIT |
u5, h5, h7 |
LL_SPI_DATA_WIDTH_32BIT |
|
LL_SPI_FIFO_TH_01DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_1_DATA |
|
LL_SPI_FIFO_TH_02DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_2_DATA |
|
LL_SPI_FIFO_TH_03DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_3_DATA |
|
LL_SPI_FIFO_TH_04DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_4_DATA |
|
LL_SPI_FIFO_TH_05DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_5_DATA |
|
LL_SPI_FIFO_TH_06DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_6_DATA |
|
LL_SPI_FIFO_TH_07DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_7_DATA |
|
LL_SPI_FIFO_TH_08DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_8_DATA |
|
LL_SPI_FIFO_TH_09DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_9_DATA |
|
LL_SPI_FIFO_TH_10DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_10_DATA |
|
LL_SPI_FIFO_TH_11DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_11_DATA |
|
LL_SPI_FIFO_TH_12DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_12_DATA |
|
LL_SPI_FIFO_TH_13DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_13_DATA |
|
LL_SPI_FIFO_TH_14DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_14_DATA |
|
LL_SPI_FIFO_TH_15DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_15_DATA |
|
LL_SPI_FIFO_TH_16DATA |
u5, h5, h7 |
LL_SPI_FIFO_THRESHOLD_16_DATA |
|
LL_I2S_AUDIOFREQ_192K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_192_KHZ |
|
LL_I2S_AUDIOFREQ_96K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_96_KHZ |
|
LL_I2S_AUDIOFREQ_48K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_48_KHZ |
|
LL_I2S_AUDIOFREQ_44K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_44_KHZ |
|
LL_I2S_AUDIOFREQ_32K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_32_KHZ |
|
LL_I2S_AUDIOFREQ_22K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_22_KHZ |
|
LL_I2S_AUDIOFREQ_16K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_16_KHZ |
|
LL_I2S_AUDIOFREQ_11K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_11_KHZ |
|
LL_I2S_AUDIOFREQ_8K |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_8_KHZ |
|
LL_I2S_AUDIOFREQ_DEFAULT |
u5, h5, h7 |
LL_I2S_MASTER_AUDIO_FREQ_DEFAULT |
|
LL_I2S_DATAFORMAT_16B |
u5, h5, h7 |
LL_I2S_DATA_FORMAT_16_BIT |
|
LL_I2S_DATAFORMAT_16B_EXTENDED |
u5, h5, h7 |
LL_I2S_DATA_FORMAT_16_BIT_EXTENDED |
|
LL_I2S_DATAFORMAT_24B |
u5, h5, h7 |
LL_I2S_DATA_FORMAT_24_BIT |
|
LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED |
u5, h5, h7 |
LL_I2S_DATA_FORMAT_24_BIT |
|
LL_I2S_DATAFORMAT_32B |
u5, h5, h7 |
LL_I2S_DATA_FORMAT_32_BIT |
|
LL_I2S_FIFO_TH_01DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_1_DATA |
|
LL_I2S_FIFO_TH_02DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_2_DATA |
|
LL_I2S_FIFO_TH_03DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_3_DATA |
|
LL_I2S_FIFO_TH_04DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_4_DATA |
|
LL_I2S_FIFO_TH_05DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_5_DATA |
|
LL_I2S_FIFO_TH_06DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_6_DATA |
|
LL_I2S_FIFO_TH_07DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_7_DATA |
|
LL_I2S_FIFO_TH_08DATA |
u5, h5, h7 |
LL_I2S_FIFO_THRESHOLD_8_DATA |
|
LL_I2S_MCLK_OUTPUT_ENABLE |
u5, h5, h7 |
LL_I2S_EnableMasterClock |
|
LL_I2S_MCLK_OUTPUT_DISABLE |
u5, h5, h7 |
LL_I2S_DisableMasterClock |
|
LL_I2S_POLARITY_HIGH |
u5, h5, h7 |
LL_I2S_CLOCK_POLARITY_HIGH |
|
LL_I2S_POLARITY_LOW |
u5, h5, h7 |
LL_I2S_CLOCK_POLARITY_LOW |
|
LL_I2S_SLAVE_FIXED_CH_LENGTH |
u5, h5, h7 |
Removed / sequence changed |
|
LL_I2S_SLAVE_VARIABLE_CH_LENGTH |
u5, h5, h7 |
Removed / sequence changed |
|
LL_I2S_CR2_ERRIE |
u5, h5, h7 |
LL_I2S_IT_TIFRE |
|
LL_I2S_CR2_RXNEIE |
u5, h5, h7 |
LL_I2S_IT_RXP |
|
LL_I2S_CR2_TXEIE |
u5, h5, h7 |
LL_I2S_IT_TXP |
|
LL_I2S_SR_BSY |
u5, h5, h7 |
Removed / sequence changed |
|
LL_I2S_SR_FRE |
u5, h5, h7 |
LL_I2S_FLAG_TIFRE |
|
LL_I2S_SR_OVR |
u5, h5, h7 |
LL_I2S_FLAG_OVR |
|
LL_I2S_SR_RXNE |
u5, h5, h7 |
LL_I2S_FLAG_RXP |
|
LL_I2S_SR_TXE |
u5, h5, h7 |
LL_I2S_FLAG_TXP |
|
LL_I2S_SR_UDR |
u5, h5, h7 |
LL_I2S_FLAG_UDR |
LL SPI macros ¶
|
HAL1 |
series |
HAL2 |
|---|---|---|
|
LL_SPI_WriteReg |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_WRITE_REG |
|
LL_SPI_ReadReg |
u5, h5, c0, l4, g4, g0, f4, h7 |
LL_SPI_READ_REG |
|
LL_I2S_WriteReg |
u5, h5, h7 |
LL_I2S_WRITE_REG |
|
LL_I2S_ReadReg |
u5, h5, h7 |
LL_I2S_READ_REG |
LL SPI structures ¶
|
HAL1 |
series |
HAL2 |
Refer to |
|---|---|---|---|
|
LL_SPI_InitTypeDef |
u5, h5, c0, l4, g4, g0, f4, h7 |
Removed / sequence changed |
|
|
LL_I2S_InitTypeDef |
u5, h5, h7 |
Removed / sequence changed |
LL SPI functions ¶
|
HAL1 |
series |
HAL2 |
Refer to |
|---|---|---|---|
|
LL_SPI_Init |
u5, h5, c0, l4, g4, g0, f4, h7 |
Sequence changed |
|
|
LL_SPI_DeInit |
u5, h5, c0, l4, g4, g0, f4, h7 |
Sequence changed |
|
|
LL_SPI_StructInit |
u5, h5, c0, l4, g4, g0, f4, h7 |
Sequence changed |
|
|
LL_SPI_IsEnabledIT_TXE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_IsEnabledIT_RXNE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_IsEnabledIT_ERR |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_DisableIT_TXE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_DisableIT_RXNE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_DisableIT_ERR |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_EnableIT_TXE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_SetDMAParity_RX |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_EnableIT_RXNE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_GetTxFIFOLevel |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_GetRxFIFOLevel |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_IsActiveFlag_BSY |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_IsActiveFlag_TXE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_IsActiveFlag_RXNE |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_SetCRCNext |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_GetRxFIFOThreshold |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_EnableIT_ERR |
c0, l4, g4, g0, f4 |
Not implemented yet in HAL2. |
|
|
LL_SPI_SetRxFIFOThreshold |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_GetDMAParity_RX |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_GetDMAParity_TX |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_SetDMAParity_TX |
c0, l4, g4, g0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_DisableIT_TSER |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_ClearFlag_TSER |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_IsActiveFlag_TSER |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_EnableIT_TSER |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_DMA_GetRegAddr |
l4, f4, g0, g4, c0 |
Not implemented yet in HAL2. |
|
|
LL_SPI_GetReloadSize |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_GetUDRDetection |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_IsEnabledIT_TSER |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_SetReloadSize |
h7 |
Not implemented yet in HAL2. |
|
|
LL_SPI_SetUDRDetection |
h7 |
Not implemented yet in HAL2. |
|
|
LL_I2S_ConfigPrescaler |
u5, h5, h7 |
LL_I2S_SetPrescaler |
|
|
LL_I2S_DeInit |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_DisableAsyncStart |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_DisableIT_ERR |
u5, h5, h7 |
LL_I2S_DisableIT_FRE |
|
|
LL_I2S_DisableIT_RXNE |
u5, h5, h7 |
LL_I2S_DisableIT_RXP |
|
|
LL_I2S_DisableIT_TXE |
u5, h5, h7 |
LL_I2S_DisableIT_TXP |
|
|
LL_I2S_EnableAsyncStart |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_EnableIT_ERR |
u5, h5, h7 |
LL_I2S_EnableIT_FRE |
|
|
LL_I2S_EnableIT_RXNE |
u5, h5, h7 |
LL_I2S_EnableIT_RXP |
|
|
LL_I2S_EnableIT_TXE |
u5, h5, h7 |
LL_I2S_EnableIT_TXP |
|
|
LL_I2S_GetChannelLengthType |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_Init |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_InitFullDuplex |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_IsActiveFlag_BSY |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_IsActiveFlag_CHSIDE |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_IsActiveFlag_RXNE |
u5, h5, h7 |
LL_I2S_IsActiveFlag_RXP |
|
|
LL_I2S_IsActiveFlag_TXE |
u5, h5, h7 |
LL_I2S_IsActiveFlag_TXP |
|
|
LL_I2S_IsEnabledAsyncStart |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_IsEnabledIT_ERR |
u5, h5, h7 |
LL_I2S_IsEnabledIT_FRE |
|
|
LL_I2S_IsEnabledIT_RXNE |
u5, h5, h7 |
LL_I2S_IsEnabledIT_RXP |
|
|
LL_I2S_IsEnabledIT_TXE |
u5, h5, h7 |
LL_I2S_IsEnabledIT_TXP |
|
|
LL_I2S_SetChannelLengthType |
u5, h5, h7 |
Removed / sequence changed |
|
|
LL_I2S_SetPrescalerLinear |
u5, h5, h7 |
LL_I2S_SetPrescalerLinear |
|
|
LL_I2S_StructInit |
u5, h5, h7 |
Removed / sequence changed |